The embodiments of the invention generally relate to transistor manufacturing and more particularly to a method of removing sidewall spacers before silicide has been formed.
In transistors, a gate sidewall spacer is generally used to space the source/drain diffusions and silicide away from the device channel region (the shallow extension implant bridges the gap). Once silicide is formed, the spacer is typically left in place where it may adversely affect subsequent processes. For example, the spacer crowds the limited area between closely spaced gates leaving inadequate room to form good contacts. Also, the presence of the spacer forces the stress liner further from the device channel thereby limiting the effectiveness of stress transfer to the channel.
The problem with simply stripping the nitride spacer after silicide formation is that etchants suitable for nitride removal also erode silicide. Use of a sacrificial nitride deposited preferentially on the silicide has been attempted but the beneficial effect of protecting the silicide tends to be overwhelmed by the need to etch longer to remove both the spacer and the additional nitride from the gate sidewall. The net result is the same or more silicide erosion than the case where no sacrificial nitride is used.
Further, a gate cap nitride is needed for embedded silicon-germanium (eSiGe) processing to prevent epitaxial silicon-germanium (SiGe) deposition on the gate polysilicon. Removal of this cap nitride with exposed silicon and SiGe results in uncontrolled recess of the silicon and SiGe since nitride etchants typically have poor selectivity to silicon and SiGe.
In view of the foregoing, an embodiment of the invention provides a method of forming an integrated circuit transistor. The method forms a gate conductor over a substrate, and simultaneously forms spacers (e.g., nitride) on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate (adjacent to the source and drain regions opposite the channel region below the gate conductor) either before or after such structures are formed in and on the substrate. Next, the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions.
Following this, the method deposits a mask over the gate conductor, the spacers, and the source and drain regions. Following this the mask is recessed to a level below a top of the gate conductor, but above the source and drain regions, such that a portion of the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions. This leaves a structure with silicided gate conductor and source/drain regions and no spacers next to the gate conductor.
These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.